1. Technical Field
The present invention generally relates to verification of optimized designs. More specifically, the present invention relates to design size reduction using ternary simulation.
2. Description of the Related Art
Many applications can benefit by reducing the size of a design representation while preserving functionality. For example, synthesis often includes an explicit objective to reduce design size and can benefit verification, since verification can often be more efficient on a reduced or smaller design. However, most techniques for design reduction tend to be rather computationally expensive, particularly those that require sequential analysis.
Ternary simulation is a technique that analyzes behavior of a design under “0”, “1”, “X” valuations to the gates of the design (where “X” is a “do not care” or undetermined value representing either “0” or “1”). By assigning values of “X” to the valuations of primary inputs and by simulating the design until a state vector is repeated, identification of gates that are constant or pairs of gates that are equivalent can be determined. Simplification of the design can be accomplished by simplifying the gates of the resulting ternary sequence accordingly. However, there is at least one fundamental weakness of ternary simulation-based reduction: it may not converge with reasonable resources on temporally “deep” designs. For instance, a design with a 64-bit counter can require 2^64 (i.e., 2 to the power of 64) time frames or iterations of a simulation before convergence is possible. This can be too computationally expensive to perform. Accordingly, there is a need for a method, a system and/or a computer program product for convergence (repetition) of ternary simulation by saturating “deep” gates to a ternary “X” and an optimization of resulting reductions under a fixed number of ternary simulation steps.